It has been proved both by theories and experiences that when stress is applied to the channel of a transistor, the semiconductor crystal lattice in the channel will have a strain, by which the carrier mobility of the transistor will be increased or reduced; however, it is also known that electrons and holes have different responses to strains of the same type. For example, it is advantageous to the increase of the hole mobility by applying a compressive stress in a longitudinal direction along which the electric current flows to cause a compressive strain on the crystal lattice in the channel region, but this accordingly reduces the electron mobility; it is advantageous to the increase of the electron mobility by applying a tensile stress in the longitudinal direction to cause a tensile strain on the crystal lattice in the channel region, but this accordingly reduces the hole mobility. With the continuous reduction in the feature size of the device, the strain channel engineering for the purpose of increasing the channel carrier mobility becomes more and more important.
However, in the prior art, the strain introduced into the channel region is very small. Since the carrier mobility increases with the increase in the stress amplitude in the transistor channel region, the performance of the transistor will be further improved if a larger stress is generated in the channel region of the transistor.
In view of the above, with respect to transistor devices, there is still a need for a new method and semiconductor structure for introducing strain.